atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 165

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

15.2.6
15.3
7647A–AVR–02/08
Data Modes
SPI Data Register – SPDR
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
15-3
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 15-2
Table 15-5.
Figure 15-3. SPI Transfer Format with CPHA = 0
Bit
Read/Write
Initial Value
and
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
Figure
and
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
CPOL Functionality
SS
SPD7
Table
MSB first (DORD = 0)
LSB first (DORD = 1)
R/W
15-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-
7
X
15-3, as done below:
SPD6
R/W
X
6
MSB
LSB
Sample (Falling)
SPD5
Sample (Rising)
R/W
Leading Edge
Setup (Falling)
Setup (Rising)
5
X
Bit 6
Bit 1
SPD4
R/W
X
4
Bit 5
Bit 2
SPD3
R/W
3
X
Bit 4
Bit 3
ATmega32/64/M1/C1
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing eDge
SPD2
Bit 3
Bit 4
R/W
X
2
Bit 2
Bit 5
SPD1
R/W
1
X
Bit 1
Bit 6
SPD0
R/W
X
0
SPI Mode
LSB
MSB
0
1
2
3
Undefined
SPDR
Figure
165