SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 107

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

5.4
Before an interrupt request that has been arbitrated is actually serviced, the status of the
current task is automatically saved on the system stack. The CPU status (PSW) is saved
together with the location at which execution of the interrupted task is to be resumed after
returning from the service routine. This return location is specified through the Instruction
Pointer (IP) and, in the case of a segmented memory model, the Code Segment Pointer
(CSP). Bit SGTDIS in register SYSCON controls how the return location is stored.
The system stack receives the PSW first, followed by the IP (unsegmented), or followed
by CSP and then IP (segmented mode). This optimizes the usage of the system stack if
segmentation is disabled.
The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request
to be serviced, so the CPU now executes on the new level. If a multiplication or division
was in progress at the time the interrupt request was acknowledged, bit MULIP in
register PSW is set to ‘1’. In this case, the return location saved on the stack is not the
next instruction in the instruction flow, but rather the multiply or divide instruction itself,
as this instruction has been interrupted and will be completed after returning from the
service routine.
Figure 5-3
The interrupt request flag of the source being serviced is cleared. The IP is loaded with
the vector associated with the requesting source (CSP is cleared in the case of
segmentation), and the first instruction of the service routine is fetched from the vector
location which is expected to branch to the service routine itself. The data page pointers
and the context pointer are not affected.
When the interrupt service routine is exited (RETI is executed), the status information is
popped from the system stack in the reverse order, taking into account the value of bit
SGTDIS.
User’s Manual
SP
a)
System Stack before
Interrupt Entry
Saving Status during Interrupt Service
Task Status Saved on the System Stack
--
--
--
Addresses
Addresses
High
Low
SP
b)
System Stack after
Interrupt Entry
(Unsegmented)
5-17
PSW
IP
--
Interrupted
Status of
Task
Interrupt and Trap Functions
b)
System Stack after
Interrupt Entry
(Segmented)
C164CM/C164SM
PSW
CSP
IP
Derivatives
V1.0, 2002-02
MCD02226
SP