SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 436

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

The EXTP (extend page) instruction allows switching to an arbitrary data page for
1 … 4 instructions without changing the current DPPs.
EXTP
MOV
MOV
The EXTS (extend segment) instruction allows switching to a 64 KByte segment
oriented data access scheme for 1 … 4 instructions without changing the current DPPs.
In this case all 16 bits of the operand address are used as segment offset, with the
segment taken from the EXTS instruction. This greatly simplifies address calculation with
continuous data, such as huge arrays in “C”.
EXTS
MOV
MOV
Note: Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC.
Short Addressing in Extended SFR (ESFR) Space
The short addressing modes of the C164CM (REG or BITOFF) implicitly access the SFR
space. The additional ESFR space would need to be accessed via long addressing
modes (MEM or [Rw]). The EXTR (extend register) instruction redirects accesses in
short addressing modes to the ESFR space for 1 … 4 instructions, so the additional
registers can be accessed this way, too.
The EXTPR and EXTSR instructions combine the DPP override mechanism with the
redirection to the ESFR space using a single instruction.
Note: Instructions EXTR, EXTPR, and EXTSR inhibit interrupts the same way as ATOMIC
Nested Locked Sequences
Each described extension instruction and the ATOMIC instruction start an internal
“extension counter” counting the effected instructions. When another extension or
ATOMIC instruction is contained in the current locked sequence, this counter is restarted
with the value of the new instruction. This allows construction of locked sequences
longer than 4 instructions.
Note: Interrupt latencies may be increased when using locked code sequences.
User’s Manual
As long as any Class B trap is pending (any of the class B trap flags in register
TFR is set) the EXTend instructions will not work. Clear the respective B trap flag
at the beginning of a B trap routine if EXT* shall be used within the routine.
instructions. Switching to the ESFR area and data page overriding are checked by
the development tools or are handled automatically.
PEC requests are not serviced during idle mode, if the IDLE instruction is part of
a locked sequence.
R15, #1
R0, [R14]
R1, [R13]
#15, #1
R0, [R14]
R1, [R13]
;The override page number is stored in R15
;The (14-bit) page offset is stored in R14
;This instruction uses the std. DPP scheme!
;The override seg. is 15 (0F’0000H..0F’FFFFH)
;The (16-bit) segment offset is stored in R14
;This instruction uses the std. DPP scheme!
22-15
System Programming
C164CM/C164SM
Derivatives
V1.0, 2002-02