SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 179

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

ALE Length Control
The length of the ALE signal and the address hold time after its falling edge are
controlled by the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to ‘1’,
external bus cycles accessing the respective address window will have their ALE signals
prolonged by half a CPU clock (1 TCL). Also, the address hold time after the falling edge
of ALE (on a multiplexed bus) will be prolonged by half a CPU clock, so the data transfer
within a bus cycle refers to the same CLKOUT edges as usual (the data transfer is
delayed by one CPU clock). This allows more time for the address to be latched.
Note: ALECTL0 is ‘1’ after reset to select the slowest possible bus cycle, the other
Figure 9-6
User’s Manual
BUS
BUS
(P0)
(P0)
ALE
WR
RD
ALECTLx are ‘0’ after reset.
ALE Length Control
Address
Address
Normal Multiplexed
Bus Cycle
Data/Instr.
Data
9-10
Setup
Address
Address
Lengthened Multiplexed
Hold
Bus Cycle
External Bus Interface
C164CM/C164SM
Data/Instr.
Data
Derivatives
V1.0, 2002-02
MCD02235M