SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 96

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

xxIC
Interrupt Control Register
Bit
GLVL
ILVL
xxIE
xxIR
The Interrupt Request Flag is set by hardware whenever a service request from its
respective source occurs. It is cleared automatically upon entry into the interrupt service
routine or upon a PEC service. In the case of PEC service, the Interrupt Request flag
remains set if the COUNT field in register PECCx of the selected PEC channel
decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC
block transfer.
Note: Modifying the Interrupt Request flag via software causes the same effects as if it
The Interrupt Enable Control Bit determines whether the respective interrupt node
takes part in the arbitration cycles (enabled) or not (disabled). The associated request
flag will be set upon a source request in any case. The occurrence of an interrupt request
can so be polled via xxIR even while the node is disabled.
Note: In this case the interrupt request flag xxIR is not cleared automatically but must be
User’s Manual
15
-
had been set or cleared by hardware.
cleared via software.
14
-
13
-
Function
Group Level
Defines the internal order for simultaneous requests of the same priority.
3:
0:
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
F
0
Interrupt Enable Control Bit
(individually enables/disables a specific source)
0:
1:
Interrupt Request Flag
0:
1:
H
H
:
:
12
-
Highest group priority
Lowest group priority
Highest priority level
Lowest priority level
Interrupt request is disabled
Interrupt Request is enabled
No request pending
This source has raised an interrupt request
11
-
10
-
(E)SFR (yyyy
9
-
8
-
5-6
xxIR xxIE
rwh
7
H
/zz
rw
6
H
)
Interrupt and Trap Functions
5
4
ILVL
rw
Reset Value: - - 00
C164CM/C164SM
3
2
Derivatives
V1.0, 2002-02
1
GLVL
rw
0
H