SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 345

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

Bit
LEC
TXOK
RXOK
EWRN
BOFF
Note: Reading the upper half of the Control Register (status partition) will clear the
User’s Manual
Status Change Interrupt value in the Interrupt Register, if it is pending. Using byte
accesses to the lower half will avoid this.
Function (Control Bits)
Last Error Code
This field holds a code indicating the type of error which last occurred on the
CAN bus. If a message has been transferred (reception or transmission)
without error, this field will be cleared.
0
1
2
3
4
5
6
7
Transmitted Message Successfully
Indicates that a message has been transmitted successfully (error free and
acknowledged by at least one other node), since this bit was last reset by the
CPU (the CAN controller does not reset this bit!).
Received Message Successfully
This bit is set each time a message has been received successfully, since
this bit was last reset by the CPU (the CAN controller does not reset this bit!).
RXOK is also set when a message is received that is not accepted (i.e.
stored).
Error Warning Status
Indicates that at least one of the error counters in the EML has reached the
error warning limit of 96.
Busoff Status
Indicates when the CAN controller is in busoff state (see EML).
No Error
Stuff Error: More than 5 equal bits in a sequence have occurred in a
part of a received message where this is not allowed.
Form Error: Wrong format in fixed format part of a received frame.
AckError: The message transmitted by this CAN controller was not
acknowledged by another node.
Bit1Error: During the transmission of a message (with the exception
of the arbitration field), the device wanted to send a recessive level
(“1”), but the monitored bus value was dominant.
Bit0Error: During the transmission of a message (or acknowledge bit,
active error flag, or overload flag), the device wanted to send a
dominant level (“0”), but the monitored bus value was recessive.
During busoff recovery this status is set each time a sequence of
11 recessive bits has been monitored. This enables the CPU to
monitor the proceeding of the busoff recovery sequence (indicates
that the bus is not stuck at dominant or continuously disturbed).
CRCError: The received CRC check sum was incorrect.
Unused code: may be written by the CPU to check for updates.
19-8
On-Chip CAN Interface
C164CM/C164SM
Derivatives
V1.0, 2002-02