SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 282

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

Compare Mode 1
Compare mode 1 is selected for register CCx by setting bit field CCMODx of the
corresponding mode control register to ‘101
When a match between the content of the allocated timer and the compare value in
register CCx is detected in this mode, interrupt request flag CCxIR is set to ‘1’ (where
connected), and the corresponding output pin CCxIO (alternate port output function) is
toggled. For this purpose, the state of the respective port output latch (not the pin) is
read, inverted, and then written back to the output latch.
Compare mode 1 allows several compare events within a single timer period. An
overflow of the allocated timer has no effect on the output pin, nor does it disable or
enable further compare events.
In order to use the respective port pin as compare signal output pin CCxIO for compare
register CCx in compare mode 1, this port pin must be configured as output, i.e. the
corresponding direction control bit must be set to ‘1’. With this configuration, the initial
state of the output signal can be programmed or its state can be modified at any time by
writing to the port output latch.
In compare mode 1 the port latch is toggled upon each compare event (see
Figure
If compare mode 1 is programmed for one of the registers CC16 … CC19, the
double-register compare mode becomes enabled for this register if the corresponding
bank 2 register is programmed to compare mode 0 (see
Mode” on Page
Note: If the port output latch is written to by software at the same time it would be altered
Compare Mode 2
Compare mode 2 is an interrupt-only mode similar to compare mode 0; but, only one
interrupt request per timer period will be generated. Compare mode 2 is selected for
register CCx by setting bit field CCMODx of the corresponding mode control register to
‘110
When a match is detected in compare mode 2 for the first time within a timer period, the
interrupt request flag CCxIR is set to ‘1’. The corresponding port pin is not affected and
can be used for general purpose IO. However, after the first match has been detected in
this mode, all further compare events within the same timer period are disabled for
compare register CCx until the allocated timer overflows. This means that after the first
match, even when the compare register is reloaded with a value higher than the current
timer value, no compare event will occur until the next timer period.
User’s Manual
B
’.
by a compare event, the software write will have priority. In this case, the
hardware-triggered change will not become effective.
Only capture/compare channels 16 … 19 and 24 … 27 are connected to pins.
16-7).
16-19).
16-16
B
’.
Capture/Compare Unit CAPCOM2
“Double-Register Compare
C164CM/C164SM
Derivatives
V1.0, 2002-02