SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 25

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

2.2.2
The following enhancements within the C164CM allow processing of a large number of
interrupt sources:
• Peripheral Event Controller (PEC): This processor is used to off-load many interrupt
• Multiple Priority Interrupt Controller: This controller allows all interrupts to be assigned
• Multiple Register Banks: This feature allows the user to specify up to sixteen general
• Interruptible Multiple Cycle Instructions: Reduced interrupt latency is provided by
The C164CM is capable of reacting very quickly to non-deterministic events because its
interrupt response time is within a very narrow range of only 5 to 10 CPU clock cycles
(in the case of internal program execution). Its fast external interrupt inputs are sampled
every CPU clock cycle and allow even very short external signals to be recognized.
The C164CM also provides an excellent mechanism to identify and process exceptions
or error conditions that arise during run-time, so called ‘Hardware Traps’. A hardware
trap causes an immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Unless another, higher prioritized, trap service is in progress, a hardware trap will
interrupt any current program execution. In turn, a hardware trap service can normally
not be interrupted by a standard or PEC interrupt.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
User’s Manual
requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap
routines by performing single-cycle interrupt-driven byte or word data transfers
between any two locations in segment 0 with an optional increment of either the PEC
source or the destination pointer. Only one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service.
any specified priority. Interrupts may also be grouped, which enables the user to
prevent similar priority tasks from interrupting each other. For each of the possible
interrupt sources, there is a separate control register which contains an interrupt
request flag, an interrupt enable flag, and an interrupt priority bitfield. After being
accepted by the CPU, an interrupt service can be interrupted only by a higher
prioritized service request. For standard interrupt processing, each of the possible
interrupt sources has a dedicated vector location.
purpose registers located anywhere in the internal RAM. A single one-machine-cycle
instruction allows register banks to switch from one task to another.
allowing multiple-cycle instructions (multiply, divide) to be interruptible.
Programmable Multiple Priority Interrupt System
2-8
Architectural Overview
C164CM/C164SM
Derivatives
V1.0, 2002-02