SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 237

no-image

SAF-C164SM

Manufacturer Part Number
SAF-C164SM
Description
16-Bit CMOS Microcontroller
Manufacturer
Infineon Technologies
Datasheet
The Data Width Selection supports the transfer of frames of any length from 2-bit
“characters” up to 16-bit “characters”. Starting with the LSB (SSCHB = ‘0’) allows
communication with ASC0 devices in synchronous mode (C166 Family) or 8051-like
serial interfaces, for instance. Starting with the MSB (SSCHB = ‘1’) allows operation
compatible with the SPI interface.
Regardless of which data width is selected and whether the MSB or the LSB is
transmitted first, the transfer data is always right aligned in registers SSCTB and
SSCRB, and the LSB of the transfer data in bit 0 of these registers. The data bits are
rearranged for transfer by the internal shift register logic. The unselected bits of SSCTB
are ignored. The unselected bits of SSCRB will be not valid and should be ignored by
the receiver service routine.
The Clock Control allows adaptation of transmit and receive behavior of the SSC to a
variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out
transmit data, while the other clock edge is used to latch in receive data. Bit SSCPH
selects the leading edge or the trailing edge for each function. Bit SSCPO selects the
level of the clock line in the idle state. Thus, for an idle-high clock, the leading edge is a
falling one, a 1-to-0 transition.
Figure 12-3 Serial Clock Phase and Polarity Options
User’s Manual
SSCPO SSCPH
0
0
1
1
MTSR/MRST
Pins
0
0
1
1
First
Bit
Shift Data
Figure 12-3
Latch Data
12-6
High-Speed Synchronous Serial Interface
provides a summary.
Transmit Data
Serial Clock
SCLK
C164CM/C164SM
Last
Derivatives
Bit
V1.0, 2002-02
MCD01960

Related parts for SAF-C164SM