SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 346

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

19.2.1
The on-chip CAN module has one interrupt output. It is connected through a
synchronization stage to a standard interrupt node in the C164CM in the same manner
as all other interrupts of the standard on-chip peripherals. All control options are
available for this interrupt, such as enabling/disabling, level and group priority, and
interrupt or PEC service (see note below). The on-chip CAN module is connected to an
XBUS interrupt control register.
As for all other interrupts, the node interrupt request flag is cleared automatically by
hardware when this interrupt is serviced (either by standard interrupt or PEC service).
Note: As a rule, CAN interrupt requests can be serviced by a PEC channel. However,
Because an interrupt request of the CAN module can be generated by various
conditions, the appropriate CAN interrupt status register must be read in the service
routine to determine the cause of the interrupt request. The interrupt identifier INTID (a
number) in the Port Control/Interrupt Register (PCIR) indicates the cause of an interrupt.
When no interrupt is pending, the identifier will have the value 00
If the value in INTID is not 00
status register is also set, the interrupt signal to the CPU is activated. The interrupt signal
(to the interrupt node) remains active until INTID becomes 00
have been serviced) or until interrupt generation is disabled (CSR.IE = ‘0’).
Note: The interrupt node is activated only upon a 0
The interrupt with the lowest number has the highest priority. If a higher priority interrupt
(lower number) occurs before the current interrupt is processed, INTID is updated and
the new interrupt overrides the last one.
INTID is also updated after the respective source request has been processed. This is
indicated by clearing the INTPND flag in the respective object’s message control register
(MCRn) or by reading the status partition of register CSR (in the case of a status change
interrupt). The updating of INTID is done by the CAN state machine and takes up to
6 CAN clock cycles, depending on current state of the state machine (1 CAN clock cycle
= 1 or 2 CPU clock cycles, as determined by the prescaler bit CPS).
Note: A worst case condition can occur when BRP = 00
User’s Manual
because PEC channels can execute only single predefined data transfers (there
are no conditional PEC transfers), PEC service can be used only if the respective
request is known to be generated by one specific source, and on condition that no
other interrupt request will be generated in between. In practice, this seems to be
rare.
signal. The CAN interrupt service routine should only be exited after INTID has
been verified to be 00
a message just received AND the CPU is executing consecutive accesses to the CAN
module. In this rare case, the maximum delay may be 26 CAN clock cycles.
The impact of this delay can be minimized by clearing bit INTPND at an early stage
CAN Interrupt Handling
H
H
.
, then there is an interrupt pending. If bit IE in the control/
19-9
H
1 transition of the CAN interrupt
AND the CAN controller is storing
On-Chip CAN Interface
H
H
(all interrupt requests
.
C164CM/C164SM
Derivatives
V1.0, 2002-02