SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 110

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

• When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or
• When instruction N reads an operand from the internal code memory, or when N is a
• In case instruction N reads the PSW and instruction N-1 has an effect on the condition
The worst case interrupt response time during internal code memory program execution
adds to 12 state times (24 TCL).
Any reference to external locations increases the interrupt response time due to pipeline
related access priorities. The following conditions must be considered:
• Instruction fetch from an external location
• Operand read from an external location
• Result write-back to an external location
Depending on where the instructions, source and destination operands are located,
there are a number of combinations. Note, however, that only access conflicts contribute
to the delay.
A few examples illustrate these delays:
• The worst case interrupt response time including external accesses will occur when
• When the above example has the interrupt vector pointing into the internal code
• When instructions N, N+1 and N+2 are executed from external memory and the
• When the above example has the interrupt vector pointing into the internal code
User’s Manual
instruction N explicitly writes to the PSW or the SP, the minimum interrupt response
time may be extended by 1 state time for each of these conditions.
call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum interrupt
response time may additionally be extended by 2 state times during internal code
memory program execution.
flags, the interrupt response time may additionally be extended by 2 state times.
instructions N, N+1 and N+2 are executed out of external memory, instructions N-1
and N require external operand read accesses, instructions N-3 through N write back
external operands, and the interrupt vector also points to an external location. In this
case, the interrupt response time is the time to perform 9 word bus accesses, because
instruction I1 cannot be fetched via the external bus until all write, fetch, and read
requests of preceding instructions in the pipeline are terminated.
memory, the interrupt response time is 7 word bus accesses plus 2 states, because
fetching of instruction I1 from internal code memory can start earlier.
interrupt vector also points to an external location, but all operands for instructions N-3
through N are in internal memory, the interrupt response time is the time needed to
perform 3 word bus accesses.
memory, the interrupt response time is 1 word bus access plus 4 states.
5-20
Interrupt and Trap Functions
C164CM/C164SM
Derivatives
V1.0, 2002-02