SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 202

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

Timer 3 in Counter Mode
Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON
to ‘001
T3IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this pin. Bit field T3I in control
register T3CON selects the triggering transition (see
Figure 10-5 Block Diagram of Core Timer T3 in Counter Mode
Table 10-5
T3I
0 0 0
0 0 1
0 1 0
0 1 1
1 X X
For counter operation, pin T3IN must be configured as input; the respective direction
control bit DPx.y must be set to ‘0’. The maximum input frequency allowed in counter
mode is
recognized correctly, its level should be held high or low for at least 8
it changes.
User’s Manual
T3IN = P5.3
T3EUD = P5.2
TxIN
TxEUD
B
’. In counter mode timer T3 is clocked by a transition at the external input pin
f
CPU
Triggering Edge for Counter Increment/Decrement
None. Counter T3 is disabled
Positive transition (rising edge) on T3IN
Negative transition (falling edge) on T3IN
Any transition (rising or falling edge) on T3IN
Reserved. Do not use this combination
/16. To ensure that a transition of the count input signal applied to T3IN is
GPT1 Core Timer T3 (Counter Mode) Input Edge Selection
TxUD
Edge
Select
XOR
Txl
0
1
TxUDE
MUX
TxR
Core Timer Tx
10-8
Up/
Down
Table
General Purpose Timer Unit
TxOTL
10-5).
C164CM/C164SM
f
CPU
Interrupt
Request
(TxIR)
To auxiliary
Timers
MCB02030c
Derivatives
cycles before
V1.0, 2002-02
x = 3