SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 62

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

If a conditional branch is not taken, there is no deviation from the sequential program
flow, and thus no extra time is required. In this case, the instruction after the branch
instruction will enter the decode stage of the pipeline at the beginning of the next
machine cycle after the decoding of the conditional branch instruction.
Cache Jump Instruction Processing
The C164CM incorporates a jump cache to optimize conditional jumps which are
processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time
to fetch the branch target instruction can be saved and thus the corresponding cache
jump instruction in most cases takes only one machine cycle.
This performance is achieved by the following mechanism:
Whenever a cache jump instruction passes through the decode stage of the pipeline for
the first time (provided that the jump condition is met), the jump target instruction is fetched
as usual, causing a time delay of one machine cycle. In contrast to standard branch
instructions, however, the target instruction of a cache jump instruction (JMPA, JMPR,
JB, JBC, JNB, JNBS) is additionally stored in the cache after having been fetched.
After each repeatedly following execution of the same cache jump instruction, the jump
target instruction is not fetched from program memory but, rather, is taken from the
cache and is injected immediately into the decode stage of the pipeline (see
A time saving jump on cache is always taken after the second and any further occurrence
of the same cache jump instruction unless an instruction having the fundamental
capability of changing the CSP register contents (JMPS, CALLS, RETS, TRAP, RETI),
or any standard interrupt has been processed during the period of time between two
following occurrences of the same cache jump instruction.
Figure 4-4
User’s Manual
FETCH
DECODE
EXECUTE
WRITEBACK
1 Machine Cycle
Cache Jump Instruction Pipelining
Cache Jmp
I
...
n+2
I
n
1st Loop Iteration
Injection
Cache Jmp
(
I
I
TARGET
INJECT
I
n
)
Cache Jmp
I
(
TARGET+1
I
I
TARGET
INJECT
4-5
)
Cache Jmp
Repeated Loop Iteration
Injection of Cached
Target Instruction
Central Processing Unit (CPU)
I
n+2
...
I
n
Cache Jmp
I
TARGET+1
I
TARGET
C164CM/C164SM
I
n
Derivatives
Cache Jmp
V1.0, 2002-02
Figure
I
I
TARGET+2
TARGET+1
I
TARGET
MCT04329
4-4).