S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 117

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
2. Reset values in emulation modes are identical to those of the target mode.
Reset
2.3.15
Freescale Semiconductor
Address 0x001C (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
RDPB
RDPA
Field
SS
ES
EX
NS
NX
ST
1
0
(2)
W
R
:
Port B reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced independent of the function used on
the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port A reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced independent of the function used on
the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
NECLK
Depen-
Mode
ECLK Control Register (ECLKCTL)
dent
0
1
0
0
1
0
7
= Unimplemented or Reserved
NCLKX2
Table 2-15. RDRIV Register Field Descriptions (continued)
1
1
1
1
1
1
1
6
Figure 2-13. ECLK Control Register (ECLKCTL)
MC9S12XE-Family Reference Manual Rev. 1.25
DIV16
0
0
0
0
0
0
0
5
EDIV4
0
0
0
0
0
0
0
4
Description
EDIV3
3
0
0
0
0
0
0
0
Chapter 2 Port Integration Module (S12XEPIMV1)
EDIV2
0
0
0
0
0
0
0
2
Access: User read/write
EDIV1
0
0
0
0
0
0
0
1
EDIV0
0
0
0
0
0
0
0
0
117
(1)