S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 512
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
S912XEP768J5MAGR
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10 000
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
13.3.2.4
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
512
Module Base + 0x0003
ACMPIE
ASCIE
Reset
Field
Field
DJM
1
0
7
W
R
DJM
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 13-10
ATD Control Register 3 (ATDCTL3)
0
7
Interrupt will be requested whenever any of the respective CCF flags is set.
= Unimplemented or Reserved
gives examples ATD results for an input signal range between 0 and 5.12 Volts.
S8C
0
6
ETRIGLE
Table 13-7. ATDCTL2 Field Descriptions (continued)
Figure 13-6. ATD Control Register 3 (ATDCTL3)
0
0
1
1
Table 13-8. External Trigger Configurations
MC9S12XE-Family Reference Manual Rev. 1.25
Table 13-9. ATDCTL3 Field Descriptions
S4C
1
5
ETRIGP
0
1
0
1
S2C
0
4
Description
Description
External Trigger Sensitivity
S1C
0
3
Falling edge
Rising edge
High level
Low level
FIFO
0
2
Freescale Semiconductor
FRZ1
0
1
FRZ0
0
0
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