S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 677
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 18
Periodic Interrupt Timer (S12PIT24B4CV2)
18.1
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules
or raise periodic interrupts. Refer to
18.1.1
18.1.2
The PIT includes these features:
18.1.3
Refer to the device overview for a detailed explanation of the chip modes.
Freescale Semiconductor
Revision
Number
V01.00
V01.01
•
•
•
•
•
•
micro time bases
Four timers implemented as modulus down-counters with independent time-out periods.
Time-out periods selectable between 1 and 2
cycles with 1 <= m <= 256 and 1 <= n <= 65536.
Timers that can be enabled individually.
Four time-out interrupts.
Four time-out trigger output signals available to trigger peripheral modules.
Start of timer channels can be aligned to each other.
Introduction
Glossary
Features
Modes of Operation
CCR
SoC
28 Apr 2005
ISR
05 Jul 2005
PIT
Revision
Date
18.6/18-690
Sections
Affected
Periodic Interrupt Timer
Interrupt Service Routine
Condition Code Register
System on Chip
clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit
modulus down-counters.
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 18-1
Table 18-1. Revision History
Acronyms and Abbreviations
- Initial Release
- Added application section.
- Removed table 1-1
for a simplified block diagram.
24
bus clock cycles. Time-out equals m*n bus clock
Description of Changes
677
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