S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 122
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.22
2.3.23
122
Address 0x0241
Address 0x0242
Write:Never, writes to this register have no effect.
Write: Anytime.
DDRT
Field
Field
PTIT
Reset
Reset
7-0
7-0
W
W
R
R
Port T input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port T data direction—
This register controls the data direction of pins 7 through 0.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
DDRT7
PTIT7
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
u
0
7
7
= Unimplemented or Reserved
DDRT6
PTIT6
u
0
6
6
Figure 2-21. Port T Data Direction Register (DDRT)
Table 2-22. DDRT Register Field Descriptions
Table 2-21. PTIT Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-20. Port T Input Register (PTIT)
DDRT5
PTIT5
u
0
5
5
DDRT4
PTIT4
u
0
4
4
Description
Description
u = Unaffected by reset
DDRT3
PTIT3
3
u
3
0
DDRT2
PTIT2
u
0
2
2
Access: User read/write
Freescale Semiconductor
DDRT1
PTIT1
u
0
1
1
Access: User read
DDRT0
PTIT0
u
0
0
0
(1)
(1)
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