S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 151

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

1. Read: Anytime.
Freescale Semiconductor
Write: Anytime.
DDRJ
DDRJ
DDRJ
DDRJ
DDRJ
DDRJ
Field
7
6
5
4
3
2
Port J data direction—
This register controls the data direction of pin 7.
The enabled CAN4 or routed CAN0 forces the I/O state to be an output. The enabled IIC0 module forces this pin to
be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling
the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 6.
The enabled CAN4 or routed CAN0 forces the I/O state to be an input. The enabled IIC0 module forces this pin to
be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling
the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 5.
The enabled CS2 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open
drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O
direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 4.
The enabled CS0 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open
drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O
direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 3.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 2.
The enabled CS1 signal forces the I/O state to be an output. In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Table 2-59. DDRJ Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
151