S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 152
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.64
152
Address 0x026B
Write: Anytime.
DDRJ
DDRJ
RDRJ
Field
Field
Reset
7-0
1
0
W
R
Port J data direction—
This register controls the data direction of pin 1.
The enabled SCI2 forces the I/O state to be an output. The DDRM bits revert to controlling the I/O direction of a pin
when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 0.
The enabled SCI3 or CS3 signal forces the I/O state to be an output. In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
RDRJ7
Port J Reduced Drive Register (RDRJ)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
RDRJ6
Table 2-59. DDRJ Register Field Descriptions (continued)
0
6
Figure 2-62. Port J Reduced Drive Register (RDRJ)
Table 2-60. RDRJ Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
RDRJ5
0
5
RDRJ4
NOTE
0
4
Description
Description
RDRJ3
3
0
RDRJ2
0
2
Access: User read/write
Freescale Semiconductor
RDRJ1
0
1
RDRJ0
0
0
(1)
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