S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 552

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA.
When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set.
Full count register access will take place in one clock cycle.
14.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)
Read: Anytime
Write: Anytime
552
Module Base + 0x0023
Module Base + 0x0024
Module Base + 0x0025
Reset
Reset
Reset
W
W
W
R
R
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
PACNT7
PACNT7
0
0
0
7
7
7
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
Figure 14-39. Pulse Accumulators Count Register 2 (PACN2)
Figure 14-40. Pulse Accumulators Count Register 1 (PACN1)
Figure 14-41. Pulse Accumulators Count Register 0 (PACN0)
PACNT6
PACNT6
0
0
0
6
6
6
MC9S12XE-Family Reference Manual Rev. 1.25
PACNT5
PACNT5
0
0
0
5
5
5
PACNT4
PACNT4
NOTE
0
0
0
4
4
4
PACNT3
PACNT3
0
0
0
3
3
3
PACNT2
PACNT2
0
0
0
2
2
2
PACNT1(9)
PACNT1
PACNT1
Freescale Semiconductor
0
0
0
1
1
1
PACNT0(8)
PACNT0
PACNT0
0
0
0
0
0
0