S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 217

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

3.4.3
CPU and XGATE accesses are watched in the memory protection unit (See MPU Block Guide). In case of
access violation, the suspect master is acknowledged with an indication of an error; the victim target will
not be accessed.
Other violations MPU is not handling are listed below.
3.4.3.1
A possible access error is flagged by the MMC and signalled to XGATE under the following conditions:
For further details refer to the XGATE Block Guide.
3.4.4
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 3-23
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
Freescale Semiconductor
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•
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XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).
XGATE accesses the register space (in case of opcode or vector fetch).
XGATE performs a write to Flash in any modes (in case of load-store access).
XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode
or vector fetch accesses).
1
Chip Access Restrictions
Chip Bus Control
).
Illegal XGATE Accesses
MC9S12XE-Family Reference Manual Rev. 1.25
Chapter 3 Memory Mapping Control (S12XMMCV4)
217