S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 557

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

14.3.2.23 Input Control Overwrite Register (ICOVW)
Read: Anytime
Write: Anytime
All bits reset to zero.
14.3.2.24 Input Control System Control Register (ICSYS)
Read: Anytime
Write: Once in normal modes
Freescale Semiconductor
Module Base + 0x002A
Module Base + 0x002B
NOVW[7:0]
Reset
Reset
Field
7:0
W
W
R
R
NOVW7
SH37
No Input Capture Overwrite
0 The contents of the related capture register or holding register can be overwritten when a new input capture
1 The related capture register or holding register cannot be written by an event unless they are empty (see
DLY7
0
0
7
7
0
0
0
0
0
1
or latch occurs.
Section 14.4.1.1, “IC
latched in the holding register.
DLY6
0
0
0
0
1
1
Table 14-29. Delay Counter Select Examples when PRNT = 1
NOVW6
SH26
Figure 14-46. Input Control Overwrite Register (ICOVW)
0
0
6
6
Figure 14-47. Input Control System Register (ICSYS)
DLY5
0
0
0
1
1
1
MC9S12XE-Family Reference Manual Rev. 1.25
Channels”). This will prevent the captured value being overwritten until it is read or
Table 14-30. ICOVW Field Descriptions
DLY4
NOVW5
SH15
0
0
1
1
1
1
0
0
5
5
DLY3
0
1
1
1
1
1
NOVW4
SH04
DLY2
0
0
4
4
1
1
1
1
1
1
Description
DLY1
NOVW3
1
1
1
1
1
1
TFMOD
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
DLY0
1
1
1
1
1
1
NOVW2
PACMX
1024 bus clock cycles
128 bus clock cycles
256 bus clock cycles
512 bus clock cycles
0
0
2
2
32 bus clock cycles
64 bus clock cycles
Delay
NOVW1
BUFEN
0
0
1
1
NOVW0
LATQ
0
0
0
0
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