S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 690

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S912XEP768J5MAGR

Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEP768J5MAGR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
modify-write instruction which writes back the “bit-wise or” of the flag_register and the mask into the
flag_register. BSET would clear all flag bits that were set, independent from the mask.
For example, to clear flag bit 0 use: MOVB #$01,PITTF.
18.6
To get started quickly with the PIT24B4C module this section provides a small code example how to use
the block. Please note that the example provided is only one specific case out of the possible configurations
and implementations.
Functionality: Generate an PIT interrupt on channel 0 every 500 PIT clock cycles.
; ******************** Start PIT Initialization *******************************************************
;******************** Main Program *************************************************************
MAIN:
;******************** Channel 0 Interupt Routine ***************************************************
CH0_ISR:
690
Application Information
ORG
LDS
MOVW
CLR
MOVB
CLR
MOVB
MOVW
MOVB
MOVB
CLI
BRA *
LDAA
MOVB
RTI
CODESTART
RAMEND
#CH0_ISR,VEC_PIT_CH0 ; Change value of channel 0 ISR adr
PITCFLMT
#$01,PITCE
PITMUX
#$63,PITMTLD0
#$0004,PITLD0
#$01,PITINTE
#$80,PITCFLMT
PITTF
#$01,PITTF
MC9S12XE-Family Reference Manual Rev. 1.25
; place the program into specific
; range (to be selected)
; load stack pointer to top of RAM
; disable PIT
; enable timer channel 0
; ch0 connected to micro timer 0
; micro time base 0 equals 100 clock cycles
; time base 0 eq. 5 micro time bases 0 =5*100 = 500
; enable interupt channel 0
; enable PIT
; clear Interupt disable Mask bit
; loop until interrupt
; 8 bit read of PIT time out flags
; clear PIT channel 0 time out flag
; return to MAIN
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