S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 182
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port E pin PE[6] can be used for either general-purpose I/O, as TAGHI input or as MODB input during
reset.
Port E pin PE[5] can be used for either general-purpose I/O, as TAGLO input, RE output or as MODA
input during reset.
Port E pin PE[4] can be used for either general-purpose I/O or as the free-running clock ECLK output
running at the Bus Clock rate or at the programmed divided clock rate. The clock output is always enabled
in emulation modes.
Port E pin PE[3] can be used for either general-purpose I/O, as LSTRB or LDS output, or as EROMCTL
input during reset.
Port E pin PE[2] can be used for either general-purpose I/O, or as RW or WE output.
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ
interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (2.3.17/119) and clearing the
I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a simple
input with a pull-up.
Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input.
XIRQ can be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so
this pin is initially configured as a high-impedance input with a pull-up.
Port E pins PE[5] and PE[6] are configured for reduced input threshold in certain modes (refer to
S12X_EBI section).
2.4.3.5
Port K pins PK[7:0] can be used for either general-purpose I/O, or with the external bus interface. In this
case Port K pins PK[6:0] are associated with the external address bus outputs ADDR22-ADDR16 and PK7
is associated to the EWAIT input.
Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).
2.4.3.6
This port is associated with the ECT module.
Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the Enhanced
Capture Timer.
2.4.3.7
This port is associated with SCI0, SCI1 and SPI0.
Port S pins PS[7:4] can be used either for general-purpose I/O, or with the SPI0 subsystem.
Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem.
Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem.
182
Port K
Port T
Port S
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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