S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 289

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

7.4.3
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU on the
SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control
registers, and all external memory.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although, they can still be executed in this mode. When executing a
hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not
disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is
momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation
does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,
if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the
BDM found a free cycle.
The BDM hardware commands are listed in
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations
are not normally in the system memory map but share addresses with the application in memory. To
distinguish between physical memory locations that share the same address, BDM memory resources are
enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM
locations unobtrusively, even if the addresses conflict with the application memory map.
Freescale Semiconductor
BACKGROUND
ACK_ENABLE
ACK_DISABLE
READ_BD_BYTE
READ_BD_WORD
READ_BYTE
READ_WORD
WRITE_BD_BYTE
WRITE_BD_WORD
WRITE_BYTE
Command
BDM Hardware Commands
Opcode
(hex)
CC
EC
D5
D6
E4
E0
E8
C4
C0
90
16-bit address
16-bit data out
16-bit address
16-bit data out
16-bit address
16-bit data out
16-bit address
16-bit data out
16-bit address
16-bit address
16-bit address
16-bit data in
16-bit data in
16-bit data in
None
None
None
Data
MC9S12XE-Family Reference Manual Rev. 1.25
Table 7-6. Hardware Commands
Enter background mode if firmware is enabled. If enabled, an ACK will be
issued when the part enters active background mode.
Enable Handshake. Issues an ACK pulse after the command is executed.
Disable Handshake. This command does not issue an ACK pulse.
Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
Read from memory with standard BDM firmware lookup table in map.
Must be aligned access.
Read from memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
Read from memory with standard BDM firmware lookup table out of map.
Must be aligned access.
Write to memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
Write to memory with standard BDM firmware lookup table in map.
Must be aligned access.
Write to memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
Table
7-6.
Chapter 7 Background Debug Module (S12XBDMV2)
Description
289