S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 458

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 10 XGATE (S12XGATEV3)
XNOR
Operation
~(RS1 ^ RS2)
~(RD ^ IMM16)⇒ RD
(translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0])
Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination
register RD.
Remark: Using R0 as a source registers will calculate the one’s complement of the other source register.
Using R0 as both source operands will fill RD with $FFFF.
CCR Effects
Code and CPU Cycles
458
N:
Z:
V:
C:
XNOR RD, RS1, RS2
XNOR RD, #IMM16
N
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to XNORH instruction for #IMM16 operations.
0; cleared.
Not affected.
Z
∆
V
0
Source Form
—
When using immediate addressing mode (XNOR RD, #IMM16), the Z-flag
of the first instruction (XNORL RD, #IMM16[7:0]) is not considered by the
second instruction (XNORH RD, #IMM16[15:8]).
⇒ Don’t rely on the Z-Flag.
C
⇒ RD
MC9S12XE-Family Reference Manual Rev. 1.25
Address
Mode
IMM8
IMM8
TRI
Logical Exclusive NOR
0
1
1
NOTE
0
0
0
0
1
1
1
1
1
0
0
1
Machine Code
RD
RD
RD
RS1
IMM16[15:8]
IMM16[7:0]
RS2
XNOR
Freescale Semiconductor
1
1
Cycles
P
P
P