DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 192

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 7: Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is
deleted.
Bit 6: Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a
frame is repeated.
Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either
repeated or deleted a frame.
Bit 3: Receive Signaling Change of State Event (RSCOS). Set when any channel selected by the Receive
Signaling Change of State Interrupt Enable registers
Bit 2: One-Second Timer (1SEC). Set on every one-second interval based on RCLKn.
Bit 1: Timer Event (TIMER). This status bit indicates that the performance monitor counters have been updated
and are available to be read by the host. The error counter update interval as determined by the settings in the
Error Counter Configuration Register (ERCNT).
Bit 0: Receive Multiframe Event (RMF)
T1: Set on increments of 1 second or 42ms based on RCLKn, or a manual latch event.
E1: Set on increments of 1 second or 62.5ms based on RCLKn, or a manual latch event.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
E1 Mode: Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is
available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled.
RESF
7
0
RLS4
Receive Latched Status Register 4
093h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
RESEM
6
0
RSLIP
5
0
192 of 310
(RSCSE1
—
4
0
through RSCSE3) changes signaling state.
RSCOS
3
0
DS26519 16-Port T1/E1/J1 Transceiver
1SEC
2
0
TIMER
1
0
RMF
0
0