DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 284

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DS26519GA2

Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26519GA2

Part # Aliases
90-26519-0A2
Figure 11-28. E1 Transmit-Side Interleave Bus Operation—BYTE Mode
TSSYNCIOn
TSSYNCIOn
TSYSCLKn
NOTE 1: 4.096MHz BUS CONFIGURATION.
NOTE 2: 8.192MHz BUS CONFIGURATION.
NOTE 3: TSSYNCIOn IS IN THE INPUT MODE (TIOCR.2 = 0).
NOTE 4: THOUGH NOT SHOWN, TCHCLKn CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD.
NOTE 5: THOUGH NOT SHOWN, TCHBLKn CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD.
TSIGn
TSIGn
TSERn
TSERn
TSERn
TSIGn
1
2
3
1
2
FR2 CH32
FR2 CH32
FRAMER 3, CHANNEL 32
FRAMER 3, CHANNEL 32
FR1 CH32
FR1 CH32
FR3 CH32
FR3 CH32
A
B
C/A
FR0 CH1
FR0 CH1
LSB
D/B
FR0 CH1
FR0 CH1
MSB
FR1 CH1
FR1 CH1
FRAMER 0, CHANNEL 1
FRAMER 0, CHANNEL 1
FR2 CH1
FR2 CH1
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BIT DETAIL
FR1 CH1
FR1 CH1
A
FR3 CH1
FR3 CH1
B
C/A
FR0 CH2
FR0 CH2
D/B
LSB
FR0 CH2
FR0 CH2
MSB
FR1 CH2
FR1 CH2
DS26519 16-Port T1/E1/J1 Transceiver
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
FR2 CH2
FR2 CH2
FR1 CH2
FR1 CH2
A
FR3 CH2
FR3 CH2
B
C/A
D/B
LSB

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