DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 217
![no-image](/images/no-image-200.jpg)
DS26519GA2
Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26519GA2.pdf
(310 pages)
Specifications of DS26519GA2
Part # Aliases
90-26519-0A2
- Current page: 217 of 310
- Download datasheet (3Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: Software-Signaling Insertion Enable for Channels 1 to 32 (CH[1:32]). These bits determine which
channels are to have signaling inserted form the Transmit Signaling registers.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address
120h is for channel 1, address 13Fh is for channel 32. TIDR25:TIDR32 are E1 mode.
0 = Do not source signaling data from the TS registers for this channel.
1 = Source signaling data from the TS registers for this channel.
(MSB)
CH16
CH24
CH32
CH8
7
C7
7
0
CH15
CH23
CH31
CH7
SSIE1, SSIE2, SSIE3, SSIE4
Software-Signaling Insertion Enable Registers 1 to 4
118h, 119h, 11Ah, 11Bh + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
TIDR1 to TIDR32
Transmit Idle Code Definition Registers 1 to 32
120h to 13Fh + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
6
C6
6
0
CH14
CH22
CH30
CH6
5
C5
5
0
CH13
CH21
CH29
CH5
4
217 of 310
C4
4
0
CH12
CH20
CH28
CH4
3
C3
CH11
CH19
CH27
3
0
CH3
2
DS26519 16-Port T1/E1/J1 Transceiver
CH10
CH18
CH26
CH2
C2
1
2
0
(LSB)
CH17
CH25
CH1
CH9
0
C1
1
0
SSIE1
SSIE2
SSIE3
SSIE4 (E1
Mode Only)
C0
0
0
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