DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 28

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

RCHBLK10/
RCHBLK11/
RCHBLK12/
RCHBLK13/
RCHBLK14/
RCHBLK15/
RCHBLK16/
RCHCLK10
RCHCLK11
RCHCLK12
RCHCLK13
RCHCLK14
RCHCLK15
RCHCLK16
RCHBLK1/
RCHBLK2/
RCHBLK3/
RCHBLK4/
RCHBLK5/
RCHBLK6/
RCHBLK7/
RCHBLK8/
RCHBLK9/
RCHCLK1
RCHCLK2
RCHCLK3
RCHCLK4
RCHCLK5
RCHCLK6
RCHCLK7
RCHCLK8
RCHCLK9
BPCLK1
BPCLK2
NAME
CLKO
AA11
AA8
E18
U20
U17
H14
R16
R17
PIN
L15
W4
M6
G8
H5
G7
H8
C3
F3
Y7
B2
Output
Output
Output
TYPE
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK.
RCHBLK[1:16]. RCHBLKn is a user-programmable output that can be forced
high or low during any of the 24 T1 or 32 E1 channels. It is synchronous with
RCLKn when the receive-side elastic store is disabled. It is synchronous with
RSYSCLKn when the receive-side elastic store is enabled. This pin is useful for
blocking clocks to a serial UART or LAPD controller in applications where not all
channels are used such as fractional service, 384kbps service, 768kbps, or
ISDN-PRI. Also useful for locating individual channels in drop-and-insert
applications, for external per-channel loopback, and for per-channel conditioning.
RCHCLK[1:16]. RCHCLKn is a dual function pin that can output either a gapped
clock or a channel clock. In gapped clock mode, RCHCLKn is a N x 64kHz
fractional clock, which is software programmable for 0 to 24 channels and the
F-bit (T1) or 0 to 32 channels (E1). In channel clock mode, RCHCLKn is a
192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each
channel. It is useful for parallel-to-serial conversion of channel data. In either
mode, RCHCLK is synchronous with RCLKn when the receive-side elastic store
is disabled or it is synchronous with RSYSCLKn when the receive-side elastic
store is enabled. The mode of RCHCLKn is determined by the RGCLKEN bit in
the RESCR register.
Backplane Clock [1:2]. Programmable clock outputs that can be set to
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. The reference to these clocks
can be RCLK[8:1] for BPCLK1 and RCLK[9:16] for BPCLK2, a 1.544MHz or
2.048MHz clock frequency derived from MCLK, or an external reference clock
(REFCLKIO). This allows system clocks to be referenced from external sources,
the T1J1E1 recovered clocks, or the MCLK oscillator.
Clock Out. Clock output pin that can be programmed to output numerous
frequencies referenced to MCLK. Frequencies available: 1.544MHz, 2.048MHz,
4.096MHz, 8.192MHz, 12.288MHz, 16.384MHz, 256kHz, and 64kHz.
GTCCR3.CLKOSEL[3:0] selects the frequency.
28 of 310
FUNCTION
DS26519 16-Port T1/E1/J1 Transceiver