DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 220

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Bit #
Name
The Transmit DDS Zero Code Registers (TDDS1–3) select which of the 24 T1 channels to insert DDS zero code
stuffing. These registers are enabled by T1.TCR2.TDDSEN.
Bits 7 to 0: Transmit Channels 1 to 24 DDS Zero Code Control Bits (CH[1:32])
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: Also used to insert Fs framing pattern in D4 framing mode.
The Transmit FDL Register (T1TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a
byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are
used.
Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the Transmit FDL Code.
Bit 6: Transmit FDL Bit 6 (TFDL6)
Bit 5: Transmit FDL Bit 5 (TFDL5)
Bit 4: Transmit FDL Bit 4 (TFDL4)
Bit 3: Transmit FDL Bit 3 (TFDL3)
Bit 2: Transmit FDL Bit 2 (TFDL2)
Bit 1: Transmit FDL Bit 1 (TFDL1)
Bit 0: Transmit FDL Bit 0 (TFDL0). LSB of the Transmit FDL Code.
0 = Do not affect data in this channel.
1 = Replace the channel with DDS Zero Code stuffing if the channel is all zeros.
(MSB)
CH16
CH24
TFDL7
CH8
7
7
0
CH15
CH23
CH7
TDDS1, TDDS2, TDDS3
Transmit DDS Zero Code Registers 1 to 3
108h, 109h, 10Ah + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
T1TFDL
Transmit FDL Register
162h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
6
TFDL6
6
0
CH14
CH22
CH6
5
TFDL5
5
0
CH13
CH21
CH5
4
220 of 310
TFDL4
4
0
CH12
CH20
CH4
3
TFDL3
CH11
CH19
3
0
CH3
2
DS26519 16-Port T1/E1/J1 Transceiver
TFDL2
CH10
CH18
CH2
1
2
0
(LSB)
CH17
CH1
CH9
0
TFDL1
1
0
TDDS1
TDDS2
TDDS3
TFDL0
0
0