DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 92

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

9.12.1 LIU Operation
The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer
coupled into the RTIPn and RRINGn pins of the DS26519. The user has the option to use partially internal
termination, software selectable for 75Ω/100Ω/110Ω/120Ω applications (in combination with an external 120Ω
resistor) or external termination. The LIU recovers clock and data from the analog signal and passes it through the
jitter attenuation mux. The DS26519 contains an active filter that reconstructs the analog received signal for the
nonlinear losses that occur in transmission. The receive circuitry also is configurable for various monitor
applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which
allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input to
the transmit side of the LIU is sent via the jitter attenuation mux to the wave shaping circuitry and line driver. The
DS26519 will drive the E1 or T1 line from the TTIPn and TRINGn pins via a coupling transformer. The line driver
can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1. The
registers that control the LIU operation are shown in
Table 9-38. Registers Related to Control of the LIU
Global Transceiver Clock Control Register 1
(GTCCR1)
Global LIU Software Reset Register 1 (GSRR1)
Global LIU Software Reset Register 2 (GSRR2)
Global LIU Interrupt Status Register 1 (GLISR1)
Global LIU Interrupt Status Register 2 (GLISR2)
Global LIU Interrupt Mask Register 1 (GLIMR1)
Global LIU Interrupt Mask Register 2 (GLIMR2)
LIU Transmit Receive Control Register (LTRCR)
LIU Transmit Impedance and Pulse Shape
Selection Register (LTIPSR)
LIU Maintenance Control Register (LMCR)
LIU Real Status Register (LRSR)
LIU Status Interrupt Mask Register (LSIMR)
LIU Latched Status Register (LLSR)
LIU Receive Signal Level Register (LRSL)
LIU Receive Impedance and Sensitivity Monitor
Register (LRISMR)
*The address shown is for LIU 1.
REGISTER
Table
ADDRESSES
92 of 310
FRAMER
1000h*
1001h*
1002h*
1003h*
1004h*
1005h*
1006h*
1007h*
00FBh
20FBh
00FEh
20FEh
00F3h
00F6h
20F6h
9-38.
MPS selections, backplane clock
selections.
Software reset control for the LIU.
Interrupt status bit for each of the 16 LIUs.
Interrupt mask register for the LIU.
T1/J1/E1 selection, output tri-state, loss
criteria.
Transmit pulse shape and impedance
selection.
Transmit maintenance and jitter
attenuation control register.
LIU real-time status register.
LIU mask registers based on latched
status bits.
LIU latched status bits related to loss, open
circuit, etc.
LIU receive signal level indicator.
LIU impedance match and sensitivity
monitor.
DS26519 16-Port T1/E1/J1 Transceiver
FUNCTION