DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 41

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

DS26519 16-Port T1/E1/J1 Transceiver
9.7
Device Interrupts
Figure 9-11
diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers GFISR1, GLISR1, and
GBISR1
to quickly identify which of the 16 transceivers is
(are) causing the interrupt(s). The host can then read the specific transceiver’s interrupt information registers (TIIR,
RIIR) and the latched status registers (LLSR, BSRBSR) to further identify the source of the interrupt(s). If TIIR or
RIIR is the source, the host reads the transmit latched status or the receive latched status registers for the source
of the interrupt. All interrupt information register bits are real-time bits that clear once the appropriate interrupt has
been serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated
status register. All latched status bits must be cleared by the host writing a “1” to the bit location of the interrupt
condition that has been serviced. Latched status bits that have been masked via the interrupt mask registers are
masked from the interrupt information registers. The interrupt mask register bits prevent individual latched status
conditions from generating an interrupt, but they do not prevent the latched status bits from being set. Therefore,
when servicing interrupts, the user should XOR the latched status with the associated interrupt mask in order to
exclude bits for which the user wished to prevent interrupt service. This architecture allows the application host to
periodically poll the latched status bits for noninterrupt conditions, while using only one set of registers.
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