DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 202

• Manufacturer Part Number: DS26519GA2
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26519GA2

• Part # Aliases: 90-26519-0A2

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Receive FIFO Overrun (ROVR)
Bit 4: Receive HDLC Opening Byte Event (RHOBT)
Bit 3: Receive Packet End Event (RPE)
Bit 2: Receive Packet Start Event (RPS)
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS)
Bit 0: Receive FIFO Not Empty Set Event (RNES)
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
—
7
0
RIM5
Receive Interrupt Mask 5 (HDLC)
0A4h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
—
6
0
ROVR
5
0
202 of 310
RHOBT
4
0
RPE
3
0
DS26519 16-Port T1/E1/J1 Transceiver
RPS
2
0
RHWMS
1
0
RNES
0
0