DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 245
DS26519GA2
Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26519GA2.pdf
(310 pages)
Specifications of DS26519GA2
Part # Aliases
90-26519-0A2
- Current page: 245 of 310
- Download datasheet (3Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real time.
Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 1: Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties
beyond the low watermark as defined by the transmit low watermark bits (TLWM).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte
available.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 6 to 0: Transmit FIFO Bytes Available (TFBA6 to TFBA0). TFBA0 is the LSB.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte.
Bit 6: Transmit HDLC Data Bit 6 (THD6)
Bit 5: Transmit HDLC Data Bit 5 (THD5)
Bit 4: Transmit HDLC Data Bit 4 (THD4)
Bit 3: Transmit HDLC Data Bit 3 (THD3)
Bit 2: Transmit HDLC Data Bit 2 (THD2)
Bit 1: Transmit HDLC Data Bit 1 (THD1)
Bit 0: Transmit HDLC Data Bit 0 (THD0). LSB of an HDLC packet data byte.
THD7
—
—
7
0
7
0
7
0
TRTS2
Transmit Real-Time Status Register 2 (HDLC)
1B1h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
TFBA
Transmit HDLC FIFO Buffer Available Register
1B3h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
THF
Transmit HDLC FIFO Register
1B4h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
TFBA6
THD6
—
6
0
6
0
6
0
TFBA5
THD5
—
5
0
5
0
5
0
245 of 310
TFBA4
THD4
—
4
0
4
0
4
0
TEMPTY
TFBA3
THD3
3
0
3
0
3
0
DS26519 16-Port T1/E1/J1 Transceiver
TFBA2
TFULL
THD2
2
0
2
0
2
0
TFBA1
TLWM
THD1
1
0
1
0
1
0
TFBA0
THD0
TNF
0
0
0
0
0
0
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