MT45W8MW16BGX-708 WT TR Micron Technology Inc, MT45W8MW16BGX-708 WT TR Datasheet - Page 11

• Manufacturer Part Number: MT45W8MW16BGX-708 WT TR
• Description: IC PSRAM 128MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 128M (8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1010-2

Page Mode READ Operation
to the legacy asynchronous READ operation. In page-
mode-capable products, an initial asynchronous read
access is performed, then adjacent addresses can be
read quickly by simply changing the low-order
address. Addresses A[3:0] are used to determine the
members of the 16-address CellularRAM page. Any
change in addresses A[4] or higher will initiate a new
t
mode access. Page mode takes advantage of the fact
that adjacent addresses can be read in a shorter period
of time than random addresses. WRITE operations do
not include comparable page mode functionality.
CLK input must be held LOW. CE# must be driven
HIGH upon completion of a page mode access. WAIT
will be driven while the device is enabled and its state
should be ignored. Page mode is enabled by setting
RCR[7] to HIGH. ADV must be driven LOW during all
page mode read accesses.
LOW longer than
Burst Mode Operation
nous READ and WRITE operations. Burst operations
consist of a multi-clock sequence that must be per-
formed in an ordered fashion. After CE# goes LOW, the
address to access is latched on the rising edge of the
next clock that ADV# is LOW. During this first clock ris-
ing edge, WE# indicates whether the operation is going
to be a READ (WE# = HIGH, Figure 8 on page 12) or
WRITE (WE# = LOW, Figure 9 on page 12).
09005aef80ec6f79 pdf/09005aef80ec6f65 zip
Burst CellularRAM 1.5_128Mb__2.fm - Rev. D 2/05 EN
AA access time. Figure 7 shows the timing for a page
Figure 7: Page Mode READ Operation
ADDRESS
Page mode is a performance-enhancing extension
During asynchronous page mode operation, the
Due to refresh considerations, CE# must not be
Burst mode operations enable high-speed synchro-
LB#/UB#
DATA
WE#
OE#
CE#
t
CEM.
(ADV# LOW)
Add[0]
t
AA
D[0]
t
Add[1]
APA
< t CEM
D[1]
t
Add[2]
APA
D[2]
t
ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY
Add[3]
APA
D[3]
DON’T CARE
11
as a fixed length or continuous. Fixed-length bursts
consist of four, eight, sixteen, or thirty-two words.
Continuous bursts have the ability to start at a speci-
fied address and burst through the entire memory.
number of clock cycles that elapse before the initial
data value is transferred between the processor and
CellularRAM device. The initial latency for READ oper-
ations can be configured as fixed or variable (WRITE
operations always use fixed latency). Variable latency
allows the CellularRAM to be configured for minimum
latency at high clock frequencies, but the controller
must monitor WAIT to detect any conflict with refresh
cycles.
worst-case access delay, including allowance for
refresh collisions. The initial latency time and clock
speed determine the latency count setting. The
boundaries of 128-word rows should not be crossed in
fixed latency mode. Fixed latency is used when the
controller cannot monitor WAIT. Fixed latency also
provides improved performance at lower clock fre-
quencies.
and de-asserts to indicate when data is to be trans-
ferred into (or out of ) the memory. WAIT will again be
asserted if the burst crosses a row boundary (variable
latency only—do not cross row boundaries when using
fixed latency). Once the CellularRAM device has
restored the previous row's data and accessed the next
row, WAIT will be de-asserted and the burst can con-
tinue (see Figure 38 on page 45).
timing penalty of the initial latency for a new burst,
burst mode can be suspended. Bursts are suspended
by stopping CLK. CLK can be stopped HIGH or LOW. If
another device will use the data bus while the burst is
suspended, OE# should be taken HIGH to disable the
CellularRAM outputs; otherwise, OE# can remain
LOW. Note that the WAIT output will continue to be
active, and as a result no other devices should directly
share the WAIT connection to the controller. To con-
tinue the burst sequence, OE# is taken LOW, then CLK
is restarted after valid data is available on the bus.
ations. CE# must not stay LOW longer than
burst suspension will cause CE# to remain LOW for
longer than
burst restarted with a new CE# LOW/ADV# LOW cycle.
The size of a burst can be specified in the BCR either
The latency count stored in the BCR defines the
Fixed latency outputs the first data word after the
The WAIT output asserts as soon as CE# goes LOW,
To access other devices on the same bus without the
The CE# LOW time is limited by refresh consider-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CEM, CE# should be taken HIGH and the
©2004 Micron Technology, Inc. All rights reserved.
8 MEG x 16
t
CEM. If a