MT45W8MW16BGX-708 WT TR Micron Technology Inc, MT45W8MW16BGX-708 WT TR Datasheet - Page 27

• Manufacturer Part Number: MT45W8MW16BGX-708 WT TR
• Description: IC PSRAM 128MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 128M (8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1010-2

Table 8:
Deep Power-Down (RCR[4])
Default = DPD Disabled
refresh-related activity. This mode is used if the system
does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted
when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150µs
to perform an initialization procedure before normal
operations can resume.
and taking CE# HIGH. DPD can be enabled using CRE
or the software sequence to access the RCR. Taking
CE# LOW for at least 10µs disables DPD and sets RCR[4] =
1; it is not necessary to write to the RCR to disable DPD.
Table 9:
09005aef80ec6f79 pdf/09005aef80ec6f65 zip
Burst CellularRAM 1.5_128Mb__2.fm - Rev. D 2/05 EN
Field Name
Bit Setting
Meaning
RCR[2]
The deep power-down bit enables and disables all
Deep power-down is enabled by setting RCR[4] = 0
BIT FIELD
0
0
0
0
1
1
1
1
RCR[1]
128Mb Address Patterns for PAR (RCR[4] = 1)
Device Identification Register Mapping
0
0
1
1
0
0
1
1
DIDR[15]
Reserved
RCR[0]
0b
—
0
1
0
1
0
1
0
1
One-quarter of die
One-quarter of die
ACTIVE SECTION
One-eighth of die
One-eighth of die
Bit Setting Version
One-half of die
One-half of die
ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY
0000b
0001b
Device Version
None of die
DIDR[14:11]
Full die
2nd
1st
27
Device Density
Page Mode Operation (RCR[7])
Default = Disabled
page mode is enabled for asynchronous READ opera-
tions. In the power-up default state, page mode is dis-
abled.
Device Identification Register
ufacturer, CellularRAM generation, and the specific
device configuration. Table 9 describes the bit fields in
the DIDR. This register is read-only.
= 01b, or through the register access software
sequence with DQ = 0002h on the third cycle.
DIDR[10:8]
ADDRESS SPACE
000000h–7FFFFFh
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
400000h–7FFFFFh
600000h–7FFFFFh
700000h–7FFFFFh
128Mb
The page mode operation bit determines whether
The DIDR provides information on the device man-
The DIDR is accessed with CRE HIGH and A[19:18]
011b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
CellularRAM 1.5
CellularRAM
Generation
DIDR[7:5]
010b
8 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
SIZE
©2004 Micron Technology, Inc. All rights reserved.
8 MEG x 16
DIDR[4:0]
Vendor ID
00011b
Micron
DENSITY
128Mb
16Mb
16Mb
64Mb
32Mb
64Mb
32Mb
0Mb