MT45W8MW16BGX-708 WT TR Micron Technology Inc, MT45W8MW16BGX-708 WT TR Datasheet - Page 6

• Manufacturer Part Number: MT45W8MW16BGX-708 WT TR
• Description: IC PSRAM 128MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 128M (8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1010-2

General Description
CMOS pseudo-static random access memories devel-
oped for low-power, portable applications. The
MT45W8MW16BGX device has a 128Mb DRAM core,
organized as 8 Meg x 16 bits. These devices include
an industry-standard burst mode Flash interface that
dramatically increases read/write bandwidth com-
pared with other low-power SRAM or Pseudo SRAM
offerings.
larRAM products incorporate a transparent self refresh
mechanism. The hidden refresh requires no additional
support from the system memory controller and has
no significant impact on device read/write perfor-
mance.
operation. The bus configuration register (BCR)
defines how the CellularRAM device interacts with the
system memory bus and is nearly identical to its coun-
terpart on burst mode Flash devices. The refresh con-
figuration register (RCR) is used to control how refresh
is performed on the DRAM array. These registers are
NOTE:
09005aef80ec6f79 pdf/09005aef80ec6f65 zip
Burst CellularRAM 1.5_128Mb__2.fm - Rev. D 2/05 EN
Micron
To operate seamlessly on a burst Flash bus, Cellu-
Two user-accessible control registers define device
Functional block diagrams illustrate simplified device operation. See ball descriptions (Table 1 on page 7); bus operations
tables (Tables 2 and 3 on page 8); and timing diagrams for detailed information.

ADV#
WAIT
CellularRAM™ products are high-speed,
WE#
OE#
UB#
CLK
CRE
CE#
LB#
A[22:0]
Control
Figure 2: Functional Block Diagram—8 Meg x 16
Logic
ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY
Refresh Configuration
Device ID Register
Bus Configuration
Address Decode
Register (RCR)
Register (BCR)
(DIDR)
Logic
6
automatically loaded with default settings during
power-up and can be updated anytime during normal
operation.
rent consumption during self refresh. CellularRAM
products include three mechanisms to minimize
standby current. Partial array refresh (PAR) enables
the system to limit refresh to only that part of the
DRAM array that contains essential data. Temperature
compensated refresh (TCR) uses an on-chip sensor to
adjust the refresh rate to match the device tempera-
ture—the refresh rate decreases at lower temperatures
to minimize current consumption during standby.
Deep power-down (DPD) enables the system to halt
the refresh operation altogether when no vital infor-
mation is stored in the device. The system config-
urable refresh mechanisms are accessed through the
RCR.
industry-standard CellularRAM 1.5 feature set estab-
lished by the CellularRAM Workgroup. It includes sup-
port for both variable and fixed latency, with three
output-device drive-strength settings, additional wrap
options, and a device ID register (DIDR).
Special attention has been focused on standby cur-
This CellularRAM device is compliant with the
8,192K x 16
MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ARRAY
DRAM
Output
Buffers
Input/
MUX
and
©2004 Micron Technology, Inc. All rights reserved.
8 MEG x 16
DQ[7:0]
DQ[15:8]