MT45W8MW16BGX-708 WT TR Micron Technology Inc, MT45W8MW16BGX-708 WT TR Datasheet - Page 8

• Manufacturer Part Number: MT45W8MW16BGX-708 WT TR
• Description: IC PSRAM 128MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 128M (8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1010-2

Table 2:
Table 3:
NOTE:
09005aef80ec6f79 pdf/09005aef80ec6f65 zip
Burst CellularRAM 1.5_128Mb__2.fm - Rev. D 2/05 EN
MODE
MODE
Read
Write
Standby
No Operation
Configuration
Register Write
Configuration
Register Read
DPD
Async Read
Async Write
Standby
No Operation
Initial Burst
Read
Initial Burst
Write
Burst Continue
Burst Suspend
Configuration
Register Write
Configuration
Register Read
DPD
1. CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
6. V
7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transi-
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word
modes. CLK must be static (HIGH or LOW) during burst suspend.
affected. When only UB# is in the select mode, DQ[15:8] are affected.
external influence.
tions from HIGH to LOW.
burst (as indicated by WAIT).
IN
= V
CC
Q or 0V; all device balls must be static (unswitched) in order to achieve standby current.
Bus Operations—Asynchronous Mode
Bus Operations—Burst Mode
Power-Down
Power-Down
Standby
Standby
POWER
POWER
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Deep
Deep
Idle
Idle
CLK
CLK
X
L
L
L
L
L
L
L
L
L
L
L
L
1
1
ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY
ADV#
ADV#
X
X
X
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
CE#
CE#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OE#
OE#
8
H
X
X
X
X
X
X
X
X
H
X
H
H
X
L
L
L
L
WE#
WE#
H
H
X
X
X
H
H
H
L
L
X
X
X
X
X
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CRE
CRE
H
H
X
L
L
L
L
X
X
H
H
X
L
L
L
L
L
L
LB#/
UB#
LB#/
UB#
X
X
X
X
L
L
L
X
X
X
X
X
X
L
L
L
L
L
WAIT
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z Config. Reg.
WAIT
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z Config. Reg.
©2004 Micron Technology, Inc. All rights reserved.
2
2
8 MEG x 16
DQ[15:0]
DQ[15:0]
Data-In or
Data-Out
Data-Out
Data-Out
Data-Out
Data-In
Data-In
Data-In
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Out
Out
X
X
3
3
NOTES
NOTES
5, 6
4, 6
4, 8
5, 6
4, 6
4, 8
4, 8
4, 8
8, 9
8, 9
4
4
7
4
4
7