MT45W8MW16BGX-708 WT TR Micron Technology Inc, MT45W8MW16BGX-708 WT TR Datasheet - Page 22

• Manufacturer Part Number: MT45W8MW16BGX-708 WT TR
• Description: IC PSRAM 128MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 128M (8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1010-2

Table 5:
WAIT Configuration (BCR[8])
Default = WAIT Transitions One Clock Before
Data Valid/Invalid
when WAIT transitions between the asserted and the
de-asserted state with respect to valid data presented
on the data bus. The memory controller will use the
WAIT signal to coordinate data transfer during synchro-
nous READ and WRITE operations. When BCR[8] = 0,
data will be valid or invalid on the clock edge immedi-
ately after WAIT transitions to the de-asserted or
asserted state, respectively (Figures 19 and 21). When A8
= 1, the WAIT signal transitions one clock period prior to
the data bus going valid or invalid (Figures 20 and 21).
WAIT Polarity (BCR[10])
Default = WAIT Active HIGH
WAIT output should be HIGH or LOW. This bit will
determine whether the WAIT signal requires a pull-up
or pull-down resistor to maintain the de-asserted
state.
NOTE:
09005aef80ec6f79 pdf/09005aef80ec6f65 zip
Burst CellularRAM 1.5_128Mb__2.fm - Rev. D 2/05 EN
DQ[15:0]
The WAIT configuration bit is used to determine
The WAIT polarity bit indicates whether an asserted
Non-default BCR setting: WAIT active LOW.
WAIT
WAIT
BCR[5]
CLK
0
0
1
1
Drive Strength
Figure 21: WAIT Configuration During Burst Operation
BCR[4]
0
1
0
1
D[0]
ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY
DRIVE STRENGTH
D[1]
(default)
Full
1/2
1/4
22
Figure 19: WAIT Configuration
NOTE:
Figure 20: WAIT Configuration
NOTE:
Data valid/invalid immediately after WAIT
transitions (BCR[8] = 0). See Figure 21.
Valid/invalid data delayed for one clock after WAIT
transitions (BCR[8] = 1). See Figure 21.
IMPEDANCE TYP (Ω)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ[15:0]
D[15:0]
Reserved
WAIT
25–30
WAIT
CLK
100
50
D[2]
CLK
Data valid (or invalid) after one clock delay
High-Z
Data immediately valid (or invalid)
High-Z
DON’T CARE
D[3]
Data[0]
USE RECOMMENDATION
C
C
104 MHz at light load
C
©2004 Micron Technology, Inc. All rights reserved.
L
L
L
= 30pF to 50pF
= 15pF to 30pF
= 15pF or lower
BCR[8] = 0
Data valid in current cycle.
BCR[8] = 1
Data valid in next cycle.
8 MEG x 16
Data[0]
Data[1]
(BCR[8] = 0)
(BCR[8] = 1)