MT45W8MW16BGX-708 WT TR Micron Technology Inc, MT45W8MW16BGX-708 WT TR Datasheet - Page 7

• Manufacturer Part Number: MT45W8MW16BGX-708 WT TR
• Description: IC PSRAM 128MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 128M (8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1010-2

Table 1:
NOTE:
09005aef80ec6f79 pdf/09005aef80ec6f65 zip
Burst CellularRAM 1.5_128Mb__2.fm - Rev. D 2/05 EN
VFBGA
ASSIGNMENT
H2, H3, H4, H5,
A3, A4, A5, B3,
E4, D3, H1, G2,
B4, C3, C4, D4,
B6, C5, C6, D5,
B1, C1, C2, D2,
G3, G4, F3, F4,
E5, F5, F6, G6,
E2, F2, F1, G1
The CLK and ADV# inputs can be tied to V
be asserted but should be ignored during asynchronous and page mode operations.
H6, E3, J4
l
J5, J6
A6
A2
G5
A1
D6
D1
B5
B2
E1
E6
J2
J3
J1
VFBGA Ball Descriptions
SYMBOL
DQ[15:0]
A[22:0]
ADV#
WAIT
V
V
WE#
OE#
UB#
CLK
CRE
RFU
CE#
LB#
V
V
CC
SS
CC
SS
Q
Q
Output
Output
Supply
Supply
Supply
Supply
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the BCR or the RCR.
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK is static LOW
during asynchronous access READ and WRITE operations and during PAGE READ
ACCESS operations.
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous READ
and WRITE operations. ADV# can be held LOW during asynchronous READ and
WRITE operations.
Control Register Enable: When CRE is HIGH, WRITE operations load the RCR or
BCR, and READ operations access the RCR, BCR, or DIDR.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is a WRITE to either a configuration register or to the memory array.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with opening a new internal page.
WAIT is asserted and should be ignored during asynchronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
Reserved for future use.
Device Power Supply: (1.70V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.70V–1.95V) Power supply for input/output buffers.
V
V
ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY
SS
SS
Q must be connected to ground.
must be connected to ground.
SS
if the device is always operating in asynchronous or page mode. WAIT will
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2004 Micron Technology, Inc. All rights reserved.
8 MEG x 16