MT45W8MW16BGX-708 WT TR Micron Technology Inc, MT45W8MW16BGX-708 WT TR Datasheet - Page 13

• Manufacturer Part Number: MT45W8MW16BGX-708 WT TR
• Description: IC PSRAM 128MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 128M (8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1010-2

Mixed-Mode Operation
READ and asynchronous READ and WRITE operations
when the BCR is configured for synchronous opera-
tion. The asynchronous READ and WRITE operations
require that the clock (CLK) remain LOW during the
entire sequence. The ADV# signal can be used to latch
the target address, or it can remain LOW during the
entire WRITE operation. CE# can remain LOW when
transitioning between mixed-mode operations with
fixed latency enabled; however, the CE# LOW time
must not exceed
tates a seamless interface to legacy burst mode Flash
memory controllers. See Figure 50 on page 57 for the
“Asynchronous WRITE Followed by Burst READ” tim-
ing diagram.
WAIT Operation
cally connected to a shared, system-level WAIT signal
(see Figure 10). The shared WAIT signal is used by the
processor to coordinate transactions with multiple
memories on the synchronous bus.
ated, WAIT goes active to indicate that the Cellular-
RAM device requires additional time before data can
be transferred. For READ operations, WAIT will remain
active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory
controller when data will be accepted into the Cellu-
larRAM device. When WAIT transitions to an inactive
state, the data burst will progress on successive clock
edges.
09005aef80ec6f79 pdf/09005aef80ec6f65 zip
Burst CellularRAM 1.5_128Mb__2.fm - Rev. D 2/05 EN
The device supports a combination of synchronous
The WAIT output on a CellularRAM device is typi-
Once a READ or WRITE operation has been initi-
Processor
Figure 10: Wired or WAIT
READY
Configuration
t
CEM. Mixed-mode operation facili-
WAIT
Device
Other
CellularRAM
WAIT
WAIT
Device
Other
ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY
External
Pull-Up/
Pull-Down
Resistor
13
(WAIT asserted and WAIT configuration BCR[8] = 1).
Bringing CE# HIGH during WAIT cycles may cause
data corruption. (Note that for BCR[8] = 0, the actual
WAIT cycles end one cycle after WAIT de-asserts, and
for row boundary crossings, start one cycle after the
WAIT signal asserts.)
= 0), the WAIT output performs an arbitration role for
READ operations launched while an on-chip refresh is
in progress. If a collision occurs, WAIT is asserted for
additional clock cycles until the refresh has completed
(see Figure 11 on page 14). When the refresh operation
has completed, the READ operation will continue nor-
mally.
WRITE burst crosses the boundary between 128-word
rows. The WAIT assertion allows time for the new row
to be accessed, and permits any pending refresh oper-
ations to be performed.
asynchronous READ and WRITE, and page READ
operations.
lularRAM device can be used in burst mode without
monitoring the WAIT signal. However, WAIT can still
be used to determine when valid data is available at
the start of the burst and at row-boundary crossings. If
WAIT is not monitored, the controller must stop burst
accesses at row boundaries and restart the burst to
access the next row.
LB#/UB# Operation
byte-wide data transfers. During READ operations, the
enabled byte(s) are driven onto the DQs. The DQs
associated with a disabled byte are put into a High-Z
state during a READ operation. During WRITE opera-
tions, any disabled bytes will not be transferred to the
RAM array and the internal value will remain
unchanged. During an asynchronous WRITE cycle, the
data to be written is latched on the rising edge of CE#,
WE#, LB#, or UB#, whichever occurs first.
during an operation, the device will disable the data
bus from receiving or transmitting data. Although the
device will seem to be deselected, it remains in an
active mode as long as CE# remains LOW.
CE# must remain asserted during WAIT cycles
When using variable initial access latency (BCR[14]
WAIT is also asserted when a continuous READ or
WAIT will be asserted but should be ignored during
By using fixed initial latency (BCR[14] = 1), this Cel-
The LB# enable and UB# enable signals support
When both the LB# and UB# are disabled (HIGH)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
8 MEG x 16