DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 11

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

October 2005 Version 1.2
FME/MS/DAC80/DS/4972
MB86064 Dual 14-bit 1GSa/s DAC
1.2
Each DAC core can be considered as two identical halves, referred to as ODD and EVEN. EVEN
samples are latched on the falling edge of Clock Output, whilst ODD samples are latched on the
rising edge.
Data can be supplied to the DAC cores either externally via the LVDS data bus or internally from the
Waveform Memory Module.
1.2.1 Data from the LVDS Interface
External data is input to the MB86064 through LVDS data ports A (pins A[14:1]) and B (pins B[14:1]).
On-chip 100 termination resistors are provided to reduce the external component count, selectable
through register SYSTEM MISC en_int_term. See Table 8 on page 11.
The data may be routed to the DAC cores through a number of paths. The most direct path routes
data straight from the LVDS input buffers to the DAC core input latches. This is the default
configuration, with the DAC input multiplexers set to accept data from the LVDS inputs according to
register WMM CONFIG, data_direct. See Table 9 below.
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Clock Output
Data (port A)
Data (port B)
SYSTEM MISC
DAC Data
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
(bit)
Data should be presented to the DAC cores as unsigned binary, 14-bit data. Bit 14 is the
MSB, and bit 1 is the LSB.
The DAC exhibits a pipeline delay through the device of 18 input clock edges.
7
Table 8: DAC Core Register: SYSTEM MISC [0x1C4] (Part 2 of 3)
en_int_term
D
D
ODD
Label
N=1
N=1
Figure 6 ODD and EVEN Data Sampling
EVEN
D
D
Internal 100R LVDS termination enable (All LVDS data inputs, loop
clock input, loop clock output and reference clock outputs)
0 = Disabled, 1 = Termination enabled (default)
N+1
N+1
D
D
ODD
N+2
N+2
D
D
EVEN
N+3
N+3
Function
Production
D
D
ODD
N+4
N+4
EVEN
D
D
N+5
N+5
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