DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 8

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

1.1.5 Loop Clock
Maintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularly
over tolerance with device-to-device variations. The MB86064 minimises potential problems through
its DDR data interface and by providing a unique loop-clock facility.
The on-chip ‘loop’ consists of an LVDS input buffer connected to an LVDS output buffer through a
programmable delay stage. This loop-through, and the associated tracking from/to the data
Page 8 of 52
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
FPGA
clkout2_clk_dly
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Table 6: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 3 of 4)
Label
The clock outputs are designed to drive a doubly-terminated LVDS line (7mA drive into a
bridged 50 load) for the best possible signal integrity. 100 termination resistors should
be connected across the Q and Q signals at each end of the differential line. Enabling the
internal LVDS terminations provides the required source termination on-chip.
Reference
Clock
Feedback
Clock
DLL/
PLL
Clock x2 (1GHz)
3
0
1
:
Clock ÷2
(500MHz)
Production
Figure 3 Loop Clock Implementation
Reg Bits
2
0
1
:
1
0
1
:
0
0
1
:
Minimum (default)
Maximum
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
MB86064 Dual 14-bit 1GSa/s DAC
Fujitsu MB86064 DAC
Increase delay to
‘retard’ data
(0 - 1.5ns, 100ps steps)
Clock Output Delay
Increase delay to
‘advance’ data
October 2005 Version 1.2
(500 MHz)
FME/MS/DAC80/DS/4972
Clock
DAC