DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 13

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

October 2005 Version 1.2
FME/MS/DAC80/DS/4972
MB86064 Dual 14-bit 1GSa/s DAC
When using the Loop Clock, the delay set by loop_clk_dly (Table 7) opposes this and effectively
advances the input data relative to the reference clock edge. Together these adjustments provide
approximately 3ns trim range for clock-to-data timing, in 100ps steps.
For further details refer to sections 1.1.4 and 1.1.5.
1.2.3 Data from the Waveform Memory Module
Data routing within the Waveform Memory Module is flexible enough to allow A and B data to be
interleaved onto a single DAC core. However, primarily the Waveform Memory Module is intended
to be loaded with waveforms and subsequently read back to drive the DAC cores. A complete
description of how to use the Waveform Memory Module is given in Section 3.
1.3
Internal current references are required to be configured according to which DAC core(s) are
enabled. These are controlled by the DAC Core Register DAC CONFIG.
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
LVDS Data Timing
Over Process
Tolerances
DAC Core Current References
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Clock
Input
Typical
Slow
Fast
-0.4ns
-0.4ns
Figure 8 LVDS Input Data Timing
+0.6ns
-0.6ns
+0.9ns
-0.9ns
+1.4ns
+1.4ns
Production
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