DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 26

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

Register bit prog_start is used to indicate the start of a write cycle to the RAMs. This bit is self
clearing. See section 3.2.2 for details of the write cycle.
3.2.2 Writing Data into the Memories
The process of writing data into the RAMs is controlled by the RAM Access Controllers, which expect
data to be presented through the serial interface in a set sequence through the WMM [EVEN/ODD]
RAM DATA registers.
The RAM Access Controllers will expect to receive the number of RAM data words specified in the
register WMM [EVEN/ODD] RAM CTRL prog_burst field. If additional RAM data words are sent, the
data will be ignored. However, if less than the specified number of data words is sent, the RAM
Access Controller will not return to the idle state until the sequence has been completed by receipt
of the correct number of RAM data words. This will corrupt the sequence in the RAM if the next RAM
data word received is not intended for that RAM element. A write sequence may be terminated early
with a software reset (see section 3.3).
The 64-bit wide WMM [EVEN/ODD] RAM DATA registers are used to transfer pre-formatted data into
the RAM address location selected by the RAM Access Controller. See Table 18. The 14-bit DAC
data should be MSB aligned to the 15th bit of the waveform sample (DAC data D14 aligned to
waveform bit 14 [15:0], i.e. register bits 0, 15, 16, 31, 32, 47, 48, 63 etc. are not used).
The following sequence could be followed,
• write the first pre-formatted RAM data word to register WMM EVEN RAM DATA
• write to register WMM EVEN RAM CTRL with bit prog_start set
• consecutively write the remaining RAM data words to register WMM EVEN RAM DATA.
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Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Table 18: Waveform Memory Module Registers: WMM [EVEN/ODD] RAM DATA [0x13/0x23]
WMM EVEN RAM
WMM ODD RAM
DATA
DATA
[31:16]
[47:32]
[63:48]
[31:16]
[47:32]
[63:48]
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
(bits)
(bits)
[15:0]
[15:0]
prog_data
prog_data
Label
Label
Production
Waveform EVEN sample word n
Waveform EVEN sample word n+2
Waveform EVEN sample word n+4
Waveform EVEN sample word n+6
Waveform ODD sample word n+1
Waveform ODD sample word n+3
Waveform ODD sample word n+5
Waveform ODD sample word n+7
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
MB86064 Dual 14-bit 1GSa/s DAC
Function
Function
October 2005 Version 1.2
FME/MS/DAC80/DS/4972