DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 2

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

Contents
1
2
3
4
5
Page 2 of 52
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 DAC Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 DAC Core Current References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 Analog Output Reference Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.7 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Programming a Read/Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Waveform Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Dual Port, Interleaved LVDS Data via the WMM . . . . . . . . . . . . . . . 22
3.2 Waveform Memory Module Operation. . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Digital Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.5 Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.6 Clock Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.7 Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 33
4.8 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.2.1
1.2.2
1.2.3
1.6.1
3.2.1
3.2.2
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DAC Core Clocks Programmable Delays . . . . . . . . . . . . . . . 5
Waveform Memory Module Clock Programmable Delay . . . 6
Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Loop Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data from the LVDS Interface. . . . . . . . . . . . . . . . . . . . . . . 11
Adjusting the Input Data Timing . . . . . . . . . . . . . . . . . . . . . 12
Data from the Waveform Memory Module . . . . . . . . . . . . . 13
Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Waveform Memory Access via the Serial Interface . . . . . . 24
Writing Data into the Memories. . . . . . . . . . . . . . . . . . . . . . 26
Production
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
MB86064 Dual 14-bit 1GSa/s DAC
October 2005 Version 1.2
FME/MS/DAC80/DS/4972