DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 22

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

3.1
By routing the external LVDS data through the Waveform Memory Module it is possible to interleave
A and B data into one of the DAC cores. To configure the device in this mode EVEN & ODD
multiplexers need to be set differently.
The DAC will now sample both input ports, for consecutive DAC samples, as the EVEN and ODD
routing through the Waveform Memory Module is not the same.
Page 22 of 52
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Clock Output
WMM EVEN MUX CTRL
WMM EVEN MUX CTRL
EVEN Data
ODD Data
mux_b_ctrl[0]
mux_a_ctrl[0]
Dual Port, Interleaved LVDS Data via the WMM
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
‘0’ (default)
‘0’ (default)
Remember to set register WMM CONFIG [0x00] bit data_direct to ‘1’ (see Table 9)
[0x11]
[0x11]
(bit 0)
(bit 4)
‘1’
‘1’
Figure 14 Interleaved Mode ODD and EVEN Data Sampling
Table 14: Configuration for Interleaved Data to DAC A
Table 15: Configuration for Interleaved Data to DAC B
Production
D
D
WMM ODD MUX CTRL
WMM ODD MUX CTRL
N+1
N=0
mux_a_ctrl[0]
mux_a_ctrl[0]
‘0’ (default)
‘0’ (default)
[0x21]
[0x21]
(bit 0)
(bit 4)
‘1’
‘1’
D
D
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
N+3
N+2
MB86064 Dual 14-bit 1GSa/s DAC
ODD data in
ODD data in
Port A
Port B
Port B
Port A
October 2005 Version 1.2
DAC A
DAC B
D
D
N+5
N+4
EVEN data in
EVEN data in
FME/MS/DAC80/DS/4972
Port B
Port A
Port A
Port B