DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 9

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

October 2005 Version 1.2
FME/MS/DAC80/DS/4972
MB86064 Dual 14-bit 1GSa/s DAC
generating device, can be incorporated in the feedback loop of a Delay-Locked Loop (DLL) or Phase-
Locked Loop (PLL) clock generator, within the generating device. This enables the system to
compensate for variations in input/output (I/O) and propagation delays in both the data generating
device and the DAC. PCB and/or cable propagation delays within the loop are also compensated for
but these are not expected to exhibit significant variation between systems. It is the I/O & on-chip
delays that will dominate.
With the loop clock implemented as illustrated in Figure 3, increasing the Clock Output delay delays
the data arriving at the DAC relative to the DAC input clock. By contrast increasing the Loop Clock
delay, within the feedback loop of the DLL/PLL, advances the relative timing.
Connections to the loop clock are via pins LPCLK_IN and LPCLK_OUT. The loop clock delay is
programmed through register SYSTEM CLOCK DELAYS, loop_clk_dly. See Table 7.
With the DAC Core Clock Delays set to their recommended values (0x00), monitoring the analog
output for a valid signal while adjusting the Clock Output and Loop Clock delays enables a diagram
of valid & invalid data latching points to be produced. An example is illustrated in Figure 4.
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
DAC CORE
DELAYS
CLOCK
[0x1B2]
loop_clk_dly
00
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Table 7: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 4 of 4)
Label
-1.5ns
It is important to make sure that the Clock Output frequency is within the specification of
the DLL/PLL. If it is too high an appropriate divided clock output should be programmed as
detailed in Table 7.
It is important not to adjust both delays simultaneously else they will counteract each other.
Either the Clock Output delay or the Loop Clock delay, or both, should be zero.
Figure 4 Finding Valid Data Eyes Using Loop Clock
Retard bits [7:4] or [3:0] (0 - 1.5ns)
11
0
1
:
Reg Bits
10
0
1
:
9
0
1
:
SYSTEM CLOCK DELAYS Register [0x1C1]
8
0
1
:
Minimum (default)
Maximum
0
(0 - 1.5ns, 100ps steps)
Advance bits [11:8] (0 - 1.5ns)
Loop Clock Delay
Production
Page 9 of 52
+1.5ns