DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 6

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

data. The delay settings are programmed through register DAC CORE CLOCK DELAYS, bits
dac_clk_dly and dac_latch_dly. Based on detailed evaluation by Fujitsu these registers should be
programmed in accordance with the recommendations given in Table 1.
Note: Bold type indicates default setting. See Appendix A.
1.1.3 Waveform Memory Module Clock Programmable Delay
A programmable delay stage is provided in the clock path prior to being applied to the Waveform
Memory Module. This delay stage is programmed through register SYSTEM CLOCK DELAYS, bits
wmm_clk_dly. See Table 2.
Page 6 of 52
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
dac_latch_dly
wmm_clk_dly
dac_clk_dly
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Table 2: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 1 of 4)
Label
Label
Label
Table 1: DAC Core Register: DAC CORE CLOCK DELAYS [0x1B2]
15
3
7
0
0
1
0
0
1
0
1
:
:
:
:
:
Production
Reg Bits
Reg Bits
Reg Bits
14
2
0
1
1
6
0
1
1
0
1
:
:
:
:
:
13
1
0
0
1
5
0
0
1
0
1
:
:
:
:
:
12
0
4
0
0
1
0
0
1
0
1
:
:
:
:
:
Minimum (* Recommended *)
Medium (default)
Maximum
Minimum (* Recommended *)
Medium (default)
Maximum
Minimum (default & recommended)
Maximum
Waveform Memory Module Clock Delay
DAC Core Analog Latch Clock Delay
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
MB86064 Dual 14-bit 1GSa/s DAC
DAC Core Digital Clock Delay
(0 - 1.5ns, 100ps steps)
(0 - 1.5ns, 100ps steps)
(0 - 1.5ns, 100ps steps)
October 2005 Version 1.2
FME/MS/DAC80/DS/4972